

-- @module : fullAdderBlock
-- @author : ben

library ieee;
use ieee.std_logic_1164.all;

entity alu is 
port (
	A, B : in bit_vector(31 downto 0);
	add_notSub : in bit;
	Sum : out bit_vector(31 downto 0)
); 
end alu;     
        
architecture structural of alu is
               
component fullAdder32 

port (A, B : in bit_vector(31 downto 0);
		Cin : in bit;
		Sum : out bit_vector(31 downto 0);
		Cout : out bit
		);

end component;

for all : fullAdder32 use entity work.fullAdder32; 
    
    signal newB : bit_vector(31 downto 0);
    signal carryIn : bit;
    signal ones : bit_vector(31 downto 0) := "11111111111111111111111111111111";  
               
begin  

newB <= B xor ones when add_notSub = '0' else B; 
carryIn <= '1' when add_notSub = '0' else '0';
ADDER: fullAdder32 port map (A, newB, carryIn, Sum);

end structural;








